veriloga
Write Verilog-A behavioral modules for analog/mixed-signal IC design (Cadence Virtuoso / Spectre). Covers 12 circuit categories. TRIGGER FIRST (before evas-sim) when the user needs to write or generate a new .va file. Key trigger phrases: "write", "create", "generate", "code", "implement" + "Verilog-A / veriloga / va / .va / behavioral model". Also triggers on: review/fix Verilog-A, "behavioral model", "veriloga", "analog HDL", circuit spec → behavioral model, "voltage-domain", "current-domain". Do NOT defer to evas-sim for authoring — evas-sim is for running an already-written file.
Installation and usage
Write Verilog-A behavioral modules for analog/mixed-signal IC design (Cadence Virtuoso / Spectre). Covers 12 circuit categories. TRIGGER FIRST (before evas-sim) when the user needs to write or generate a new .va file. Key trigger phrases: "write", "create", "generate", "code", "implement" + "Verilog-A / veriloga / va / .va / behavioral model". Also triggers on: review/fix Verilog-A, "behavioral model", "veriloga", "analog HDL", circuit spec → behavioral model, "voltage-domain", "current-domain". Do NOT defer to evas-sim for authoring — evas-sim is for running an already-written file.
ইনস্টল করার পর, টার্মিনালে নিচের কমান্ড চালিয়ে আপনি এই স্কিল ব্যবহার করতে পারবেন:
skills use veriloga