home/categories/framework-internals/mindrally-skills-fpga-skill-md
framework-internalsdevelopment

fpga

FPGA development guidelines covering Vivado, SystemVerilog, timing closure, AXI interfaces, and hardware optimization.

Mindrally
maintainer
Mindrally
Updated 1/23/2026
Stars
59
Forks
5
quick start

Installation and usage

FPGA development guidelines covering Vivado, SystemVerilog, timing closure, AXI interfaces, and hardware optimization.

Installation
$ install --globalskills.sh
Usage

Once installed, you can use this skill by running the following command in your terminal:

skills use fpga