dotenv-integration
Integrate dotenv for environment variable loading with validation and type coercion.
Integrate dotenv for environment variable loading with validation and type coercion.
Generate .shellcheckrc configuration with appropriate rules, exclusions, and severity settings for shell script linting.
Validate compliance during migration with rule checking, audit trails, and security control validation
Validate functional equivalence after migration with side-by-side comparison and behavioral verification
Deep static analysis of codebases for quality, complexity, and migration readiness assessment
Formal verification using Certora Prover with CVL specification language. Supports invariant rules, parametric verification, ghost variables, and counterexample analysis for mathematical proof of contract correctness.
Configure electron-updater with code signing verification, delta updates, staged rollouts, and multiple update channels for Electron applications
Validate EV code signing certificate chain and timestamp for Windows SmartScreen
Configure Sparkle framework for macOS auto-updates with appcast, delta updates, and code signing
Configure visual regression testing with Percy, Chromatic, or custom screenshot comparison
Automated compliance validation skill for GAAP and IFRS accounting standards with codification references
AP style compliance, grammar checking, and PR writing assistance
MISRA C/C++ static analysis and compliance checking
Pre-Startup Safety Review checklist generation skill for startup readiness verification
Format proofs and algorithms in publication-quality LaTeX
Verify correctness of compiler optimizations using formal methods
Interface with Coq proof assistant for formal verification
Validate and standardize mathematical notation
Regulatory compliance skill for ISO nanotechnology standards verification and documentation
Minimum-weight perfect matching decoder skill for surface code error correction
Review clinical documentation and assigned codes for accuracy, compliance, and optimization, identifying documentation improvement opportunities and coding errors
RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.
Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.