framework-internalsdevelopment
fpga-design
Patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis, and verification. Covers both traditional HDL and modern HLS approaches. Use when ", " mentioned.
maintainer
omer-metin
์
๋ฐ์ดํธ๋จ 2026. 1. 22.
์คํ
53
ํฌํฌ
10
quick start
Installation and usage
Patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis, and verification. Covers both traditional HDL and modern HLS approaches. Use when ", " mentioned.
์ค์น
$ install --globalskills.sh
์ฌ์ฉ๋ฒ
์ค์น ํ ํฐ๋ฏธ๋์์ ๋ค์ ๋ช ๋ น์ ์คํํ์ฌ ์ด ์คํฌ์ ์ฌ์ฉํ ์ ์์ต๋๋ค:
skills use fpga-design