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verilog-sv-language

Name: verilog-sv-language
Author: a5c-ai

Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.

查看源碼 code-quality

maintainer

a5c-ai

更新於 3/25/2026

星標

538

分支

quick start

Installation and usage

Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.

安裝

$ install --globalskills.sh

使用

安裝後，您可以通過在終端運行以下命令來使用此技能：

skills use verilog-sv-language