framework-internalsdevelopment
fpga-design
Patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis, and verification. Covers both traditional HDL and modern HLS approaches. Use when ", " mentioned.
maintainer
omer-metin
更新於 1/22/2026
星標
53
分支
10
quick start
Installation and usage
Patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis, and verification. Covers both traditional HDL and modern HLS approaches. Use when ", " mentioned.
安裝
$ install --globalskills.sh
使用
安裝後，您可以通過在終端運行以下命令來使用此技能：
skills use fpga-design