framework-internalsdevelopment
fpga
FPGA development guidelines covering Vivado, SystemVerilog, timing closure, AXI interfaces, and hardware optimization.
maintainer
Mindrally
更新於 1/23/2026
星標
59
分支
5
quick start
Installation and usage
FPGA development guidelines covering Vivado, SystemVerilog, timing closure, AXI interfaces, and hardware optimization.
安裝
$ install --globalskills.sh
使用
安裝後，您可以透過在終端機執行以下指令來使用此技能：
skills use fpga