Apply Effective Java (2nd edition) concurrency best practices when writing or reviewing multi-threaded Java code: synchronization/visibility, avoiding excessive locking, executors, concurrency utilities, thread-safety docs, lazy init, scheduler independence, and avoiding thread groups.
Safely switch between NAG, gfortran, and Intel compilers when building MAPL
Xilinx 全工具链综合助手，覆盖从零到一的完整 FPGA/MPSoC 工程构建，包括： - Vivado：硬件设计、Block Design、IP 配置、XDC 约束、综合实现、比特流生成 - Vitis HLS：C/C++ 高层次综合，生成自定义 IP 核 - Vitis Unified IDE（2022.x+）：嵌入式软件开发，Platform/Domain/Application 创建，XSCT 脚本 - PetaLinux：嵌入式 Linux 系统构建，BSP 配置，内核/rootfs 定制，启动镜像生成 - 器件支持：Zynq UltraScale+ MPSoC（EG/EV 全系及 ZCU10x 评估板）、Versal、纯 FPGA（UltraScale+/UltraScale/7 系列） 只要用户提到以下任何内容，请立即使用本 skill： vivado、vitis、hls、高层次综合、vitis_hls、petalinux、zynq、ultrascale、fpga、mpsoc、xsa、比特流、 block design、综合、实现、xdc、约束、IP核、AXI、嵌入式软件、裸机程序、linux镜像、bsp、设备树、 jesd204、jesd204b、jesd204c、204b升级204c、204b迁移、高速串行、DAC、ADC、AD9144、AD9250、AD9680、 grpc、protobuf、rpc、远程调用、上位机通信、petalinux grpc、嵌入式 rpc、zmq 迁移 grpc、udmabuf、axi dma 上位机 请在用户描述任何 Xilinx/AMD FPGA 硬件或软件设计任务时主动使用本 skill。
Unified GPU kernel operator generation and optimization skill. Automatically detects the target repository type (FlagGems, vLLM, or general Python/Triton) and dispatches to the appropriate specialized sub-skill. Includes operator generation, MCP-based iterative optimization, and feedback submission sub-skills. Use this skill when the user wants to generate or optimize a GPU kernel operator, create a Triton kernel, or says things like "generate an operator", "create a kernel for X", "optimize triton kernel", or "/kernelgen-flagos".
Generate new Kastell components from templates. Creates boilerplate for CLI commands, audit checks, providers, and MCP tools following current architecture (commands thin, core fat, adapters dispatch).
Implement deterministic UTF-8, grapheme segmentation, width policy, and wrapping primitives.
MAPL error handling macros and best practices
Upgrade .NET projects to newer versions. Use when upgrading TargetFramework in csproj/vbproj/fsproj files, migrating between .NET versions, configuring global.json, pinning SDK versions, updating CI/CD pipelines for .NET, or troubleshooting .NET upgrade issues.
Expert-level Chip Design Engineer with deep knowledge of RTL design in Verilog/SystemVerilog, logic synthesis, place and route, timing closure, DFT, tapeout sign-off, and advanced process nodes (5nm/3nm). Expert-level Chip Design Engineer with deep knowledge... Use when: chip-design, rtl, verilog, systemverilog, synopsys.
Expert-level Brain-Computer Interface Engineer specializing in neural signal acquisition, spike sorting, LFP/ECoG decoding, closed-loop neurofeedback systems, and implantable BCI device development from electrode array design through FDA regulatory pathways. Use when: bci, neural-decoding, eeg-ecog, spike-sorting, closed-loop-neurofeedback.
Generate TBD files for frameworks from any platform runtime
Expert-level PCB Hardware Engineer with deep knowledge of high-speed PCB design, signal integrity, power integrity, EMI/EMC compliance, DFM, and manufacturing output (Gerber, assembly drawings). Expert-level PCB Hardware Engineer with deep knowledge of... Use when: pcb-design, signal-integrity, emc-emi, high-speed-design, dfm.
PyTorch expert: nn.Module, training loops, distributed training (DDP), mixed precision, FSDP, torch.compile, AMP, torch.jit, TorchScript, ONNX export, custom autograd functions.
A senior mineral processing engineer with 15+ years experience in ore concentration and metallurgical operations, specializing in crushing, grinding, flotation, gravity separation, and concentrate recovery optimization. Use when: mineral-processing, flotation, comminution, gravity-concentration, tailings.
Expert-level Quantum Physicist specializing in superconducting and spin-qubit hardware, cryogenic system operation, qubit fabrication, coherence characterization (T1/T2/T2*), pulse-level gate engineering, and hardware-layer quantum error correction. Use when: qubit-fabrication, transmon, spin-qubit, t1-t2-coherence, cryogenic, drag-calibration, surface-code, surface-code-threshold, random-benchmarking, crosstalk, t1-diagnosis.
Elite Embedded Systems Engineer skill with expertise in firmware development (C/C++), RTOS (FreeRTOS, Zephyr), microcontroller programming (ARM, ESP32, STM32), hardware interfaces (I2C, SPI, UART), and IoT connectivity. Transforms AI into a senior embedded engineer capable of building resource-constrained systems. Use when: embedded-systems, firmware, rtos, microcontrollers, iot, hardware-interfaces.
CUDA expert: GPU kernel programming, memory management (global/shared/local), warp divergence, stream concurrency, cuBLAS/cuFFT integration. Use when writing GPU-accelerated code with CUDA.
Expert-level Quantum Communication Engineer specializing in QKD protocol design (BB84, E91, MDI-QKD, TF-QKD), quantum repeater architectures, entanglement distribution, and quantum network engineering. Expert-level Quantum Communication Engineer specializing... Use when: qkd, bb84, tf-qkd, quantum-repeater, entanglement-distribution.
Expert-level Nuclear Operator skill with deep knowledge of reactor operations, nuclear safety protocols, radiation protection standards, emergency response procedures, and regulatory compliance. Expert-level Nuclear Operator skill with deep knowledge of... Use when: nuclear, reactor-operation, radiation-protection, safety, energy.
Build production ML systems with PyTorch 2.x, TensorFlow, and modern ML frameworks. Implements model serving, feature engineering, A/B testing, and monitoring. Use PROACTIVELY for ML model deployment, inference optimization, or production ML infrastructure.
Senior hydrogen fuel cell engineer specializing in PEMFC stack design, membrane electrode assembly development, and hydrogen system integration. Senior hydrogen fuel cell engineer specializing in PEMFC stack design, membrane electrode assembly development,... Use when: hydrogen, fuel-cell, PEMFC, electrolyzer, green-hydrogen.
